Conventional semiconductor device packages are typically multi-layered structures. A conventional semiconductor device package may include, for example, a bottom layer of encapsulant material, a carrier, a semiconductor die, and a top layer of encapsulant material. In addition to being located above and beneath the semiconductor die and carrier, the encapsulant material of a conventional semiconductor device package may also laterally surround the semiconductor device and the carrier. In addition, a conventional semiconductor device package typically includes input/output elements to facilitate electrical connection of the semiconductor device thereof with external electronic components.
Leads are an example of conventional input/output elements. Leads typically contribute to the dimensions of the footprint of a conventional semiconductor device package and, thus, consume an undesirably large amount of real estate upon a substrate (e.g., a circuit board) to which the semiconductor device package is to be secured and electrically connected.
Other examples of such input/output elements include pins, solder balls or other discrete conductive structures (e.g., bumps, balls, columns, etc.), which contribute to the height of a conventional semiconductor device package. When coupled with the thicknesses that conventional encapsulants and carriers impart to the overall thickness of a conventional semiconductor device package, the added heights of such discrete conductive structures may result in a semiconductor device package which will protrude an undesirably large distance from a carrier substrate to which it is secured and electrically connected.
In order to keep up with the trend toward ever-decreasing the dimensions of electronic devices, various technologies have been developed to decrease the dimensions of packaged semiconductor devices. The result of many of these technologies is the “chip-scale package” (CSP), a packaged semiconductor device with lateral dimensions that are roughly the same as (i.e., slightly larger than) the corresponding lateral dimensions of the semiconductor die thereof.
Due to the relatively small, semiconductor die-dependent, lateral dimensions of CSPs, they are often formed at the so-called “wafer-scale,” meaning that packaging occurs prior to severing the semiconductor devices from a wafer or other large-scale substrate. Packaging semiconductor devices at the wafer-scale avoids the difficulties that may otherwise be associated with handling such small components during chip-scale packaging thereof.
Such wafer-scale packaging may include the formation of redistribution layers (RDL), which may rearrange or effectively expand the connection pattern of bond pads on the active surface of the semiconductor device to a redistributed connection pattern which is more suitable for connection to a substrate.
A semiconductor device including RDL is disclosed in U.S. Pat. No. 7,728,437 to Choi et al. Choi discloses a semiconductor package which includes a terminal disposed at intervals equal to or greater than a minimum pitch. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, with redistribution layer patterns formed under the semiconductor chip. Each redistribution layer includes a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part. An encapsulation layer surrounds at least a top surface of the semiconductor chip, and a patterned insulating layer is formed below the redistribution layer patterns and exposes at least parts of the second parts of the redistribution layer patterns.
Further developments in methods of making electronic devices with redistribution layers are still desired, however.